Engineering managers agree that hardware/software co-design has become a key first step in future design projects.
At the recent panel discussion of the third US East Coast EDAC (EDA Conference), many senior engineering managers discussed the issue. They suggest that there are still many unsatisfactory things about the current hardware and software collaborative design approach.
Part of the question is how to determine the collaborative design. Rich McAndrew, president of startup Siliance, says that system-level design, verification, and validation require a consistent approach. "Complexity is driving the need for hardware/software co-design," McAndrew said. "At the moment, it's essentially a methodological problem."
D. Sreenivasa Rao, senior manager of systems-level integration at Analog Devices, points out that "the design of the consumer electronics era has changed everything." In last year's panel discussion, participants urged suppliers to catch up with consumer electronics. The requirements of the times.
Rao is responsible for the chip-level and system integration of consumer and communications system-on-a-chip. He said that even if the entire system had a collaborative design, the system-on-chip could not be successful. “It is important to apply hardware/software co-design from the beginning of the design project. However, current tools, while allowing for higher levels of extraction, do not handle such detailed information that can constitute or destroy the design at the register transfer level.
"Now we can't combine a model with no time-tested benchmarks with a timed RTL simulation," Rao said, "it's best to apply a modular approach to system-level modeling."
Rao notes that in the current design tools, there are two major flaws: algorithmic verification capabilities and C to RTL validation. “In analog devices, hardware engineers don’t just politely point the way to software design engineers in the hallway. At the beginning of the hardware/software co-design approach, the nature of short time-to-market and the Moore's Law of working effectively together Will push both sides," he said.
Rao also requires design engineers to be able to identify subsystems in system-on-chip designs and to conceive the form of extracting them. Rao's role at ADI is to handle the design reuse of IP modules as part of a three-phase plan, detailing his work in a paper he wrote to the Quality Management Center magazine.
Bob Supnik, vice president of engineering at SiCortex, believes that while languages ​​like System C can solve some system-level behavioral extraction problems, there are still "significant differences between three to four factors between RTL speed simulation and SystemC."
Supnik said he has begun applying a novel hardware/software co-design approach at SiCortex to minimize unnecessary software programs, increasing the speed and power consumption of new servers.
Supnik, a senior engineer involved in the VAX microprocessor Alpha project project chip design, added, "There is no more proprietary language, they are economically meaningless."
He also supports Rao's view of the system-level design module approach. Sputnik said, "Even if you introduce multiple cores in your current chip design, you must first solve the hardware/software co-design challenge of a core, and then you can solve the co-design challenges of the four cores,"
Vlad Kheyfets, Teradyne's chief engineer and SystemC modeling designer, believes that hardware co-verification has been done in RTL. “Because it is too specific to the specific process technology, the simulation will not work.†He also asked for better tools for the C to RTL validation method.
Ian Kersley, president, adds that the goal of collaborative design is clear: "First, you can accelerate the development of system-driven software; second, you can increase confidence in the hardware before the convection; and third, simplify the integration of hardware/software. â€
At the recent panel discussion of the third US East Coast EDAC (EDA Conference), many senior engineering managers discussed the issue. They suggest that there are still many unsatisfactory things about the current hardware and software collaborative design approach.
Part of the question is how to determine the collaborative design. Rich McAndrew, president of startup Siliance, says that system-level design, verification, and validation require a consistent approach. "Complexity is driving the need for hardware/software co-design," McAndrew said. "At the moment, it's essentially a methodological problem."
D. Sreenivasa Rao, senior manager of systems-level integration at Analog Devices, points out that "the design of the consumer electronics era has changed everything." In last year's panel discussion, participants urged suppliers to catch up with consumer electronics. The requirements of the times.
Rao is responsible for the chip-level and system integration of consumer and communications system-on-a-chip. He said that even if the entire system had a collaborative design, the system-on-chip could not be successful. “It is important to apply hardware/software co-design from the beginning of the design project. However, current tools, while allowing for higher levels of extraction, do not handle such detailed information that can constitute or destroy the design at the register transfer level.
"Now we can't combine a model with no time-tested benchmarks with a timed RTL simulation," Rao said, "it's best to apply a modular approach to system-level modeling."
Rao notes that in the current design tools, there are two major flaws: algorithmic verification capabilities and C to RTL validation. “In analog devices, hardware engineers don’t just politely point the way to software design engineers in the hallway. At the beginning of the hardware/software co-design approach, the nature of short time-to-market and the Moore's Law of working effectively together Will push both sides," he said.
Rao also requires design engineers to be able to identify subsystems in system-on-chip designs and to conceive the form of extracting them. Rao's role at ADI is to handle the design reuse of IP modules as part of a three-phase plan, detailing his work in a paper he wrote to the Quality Management Center magazine.
Bob Supnik, vice president of engineering at SiCortex, believes that while languages ​​like System C can solve some system-level behavioral extraction problems, there are still "significant differences between three to four factors between RTL speed simulation and SystemC."
Supnik said he has begun applying a novel hardware/software co-design approach at SiCortex to minimize unnecessary software programs, increasing the speed and power consumption of new servers.
Supnik, a senior engineer involved in the VAX microprocessor Alpha project project chip design, added, "There is no more proprietary language, they are economically meaningless."
He also supports Rao's view of the system-level design module approach. Sputnik said, "Even if you introduce multiple cores in your current chip design, you must first solve the hardware/software co-design challenge of a core, and then you can solve the co-design challenges of the four cores,"
Vlad Kheyfets, Teradyne's chief engineer and SystemC modeling designer, believes that hardware co-verification has been done in RTL. “Because it is too specific to the specific process technology, the simulation will not work.†He also asked for better tools for the C to RTL validation method.
Ian Kersley, president, adds that the goal of collaborative design is clear: "First, you can accelerate the development of system-driven software; second, you can increase confidence in the hardware before the convection; and third, simplify the integration of hardware/software. â€
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